Regviz

Nordic Semiconductor /nrf52 /SAADC /INTEN

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INTEN

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Nordic Semiconductor/nrf52/SAADC/INTEN#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Disabled)STARTED 0 (Disabled)END 0 (Disabled)DONE 0 (Disabled)RESULTDONE 0 (Disabled)CALIBRATEDONE 0 (Disabled)STOPPED 0 (Disabled)CH0LIMITH 0 (Disabled)CH0LIMITL 0 (Disabled)CH1LIMITH 0 (Disabled)CH1LIMITL 0 (Disabled)CH2LIMITH 0 (Disabled)CH2LIMITL 0 (Disabled)CH3LIMITH 0 (Disabled)CH3LIMITL 0 (Disabled)CH4LIMITH 0 (Disabled)CH4LIMITL 0 (Disabled)CH5LIMITH 0 (Disabled)CH5LIMITL 0 (Disabled)CH6LIMITH 0 (Disabled)CH6LIMITL 0 (Disabled)CH7LIMITH 0 (Disabled)CH7LIMITL

DONE=Disabled, CH0LIMITL=Disabled, RESULTDONE=Disabled, CH5LIMITL=Disabled, CH1LIMITL=Disabled, CALIBRATEDONE=Disabled, STARTED=Disabled, CH2LIMITH=Disabled, CH1LIMITH=Disabled, CH4LIMITL=Disabled, CH5LIMITH=Disabled, CH7LIMITL=Disabled, CH7LIMITH=Disabled, CH3LIMITL=Disabled, CH6LIMITL=Disabled, CH3LIMITH=Disabled, CH2LIMITL=Disabled, CH0LIMITH=Disabled, CH6LIMITH=Disabled, END=Disabled, CH4LIMITH=Disabled, STOPPED=Disabled

Description

Enable or disable interrupt

Fields

STARTED

Enable or disable interrupt for STARTED event

0 (Disabled): Disable

1 (Enabled): Enable
END

Enable or disable interrupt for END event

0 (Disabled): Disable

1 (Enabled): Enable
DONE

Enable or disable interrupt for DONE event

0 (Disabled): Disable

1 (Enabled): Enable
RESULTDONE

Enable or disable interrupt for RESULTDONE event

0 (Disabled): Disable

1 (Enabled): Enable
CALIBRATEDONE

Enable or disable interrupt for CALIBRATEDONE event

0 (Disabled): Disable

1 (Enabled): Enable
STOPPED

Enable or disable interrupt for STOPPED event

0 (Disabled): Disable

1 (Enabled): Enable
CH0LIMITH

Enable or disable interrupt for CH[0].LIMITH event

0 (Disabled): Disable

1 (Enabled): Enable
CH0LIMITL

Enable or disable interrupt for CH[0].LIMITL event

0 (Disabled): Disable

1 (Enabled): Enable
CH1LIMITH

Enable or disable interrupt for CH[1].LIMITH event

0 (Disabled): Disable

1 (Enabled): Enable
CH1LIMITL

Enable or disable interrupt for CH[1].LIMITL event

0 (Disabled): Disable

1 (Enabled): Enable
CH2LIMITH

Enable or disable interrupt for CH[2].LIMITH event

0 (Disabled): Disable

1 (Enabled): Enable
CH2LIMITL

Enable or disable interrupt for CH[2].LIMITL event

0 (Disabled): Disable

1 (Enabled): Enable
CH3LIMITH

Enable or disable interrupt for CH[3].LIMITH event

0 (Disabled): Disable

1 (Enabled): Enable
CH3LIMITL

Enable or disable interrupt for CH[3].LIMITL event

0 (Disabled): Disable

1 (Enabled): Enable
CH4LIMITH

Enable or disable interrupt for CH[4].LIMITH event

0 (Disabled): Disable

1 (Enabled): Enable
CH4LIMITL

Enable or disable interrupt for CH[4].LIMITL event

0 (Disabled): Disable

1 (Enabled): Enable
CH5LIMITH

Enable or disable interrupt for CH[5].LIMITH event

0 (Disabled): Disable

1 (Enabled): Enable
CH5LIMITL

Enable or disable interrupt for CH[5].LIMITL event

0 (Disabled): Disable

1 (Enabled): Enable
CH6LIMITH

Enable or disable interrupt for CH[6].LIMITH event

0 (Disabled): Disable

1 (Enabled): Enable
CH6LIMITL

Enable or disable interrupt for CH[6].LIMITL event

0 (Disabled): Disable

1 (Enabled): Enable
CH7LIMITH

Enable or disable interrupt for CH[7].LIMITH event

0 (Disabled): Disable

1 (Enabled): Enable
CH7LIMITL

Enable or disable interrupt for CH[7].LIMITL event

0 (Disabled): Disable

1 (Enabled): Enable

Links

()

Register License

Copyright © 2010 - 2021, Nordic Semiconductor ASA All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.

  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

  3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data